Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V
Did you miss the poster session by Eclipse Foundation’s Frédéric Desbiens and Akif Ejaz from 10xEngineers at the RISCV Europe Summit? We’ve got you covered!
Did you miss the poster session by Eclipse Foundation’s Frédéric Desbiens and Akif Ejaz from 10xEngineers at the RISCV Europe Summit? We’ve got you covered!
Join the OpenHW Foundation, CircuitSutra Technologies and RISE-DA for Advanced D&V flow using virtual prototype + high-level synthesis for RISC-V based SoC.
See how shift-left methodologies and Agentic AI Spec-to-Silicon flow accelerate HW/SW integration and validation at multiple abstraction levels.
Why buy a bottle when you can have your own keg? Open source hardware might not shout “free beer” but the new Unified RISC-V IP Access Platform, maintained by OpenHW Foundation, is just that – free recipes for your own free-flowing beer. From CVA6 superscalers to UVM support on Verilator, Chips JU project TRISTAN has united Europe’s biggest industry players with academia to move open source semiconductors from the lab to the real world. Now with the UAP, you can benefit from all of this hard work. In this talk, you’ll get uncensored access to recent advancements in European RISC-V, and a demonstration of how you can immediately leverage industry-ready open source designs from projects across Europe, all explained with glorious beer.
Join Dr Li Chen and Christopher Elash, from the University of Saskatchewan, to explore how their STARRLab team is taking RISC-V from the lab to orbit, with a fully taped-out, space-ready ASIC based on OpenHW Foundation’s CORE-V-MCU.