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Using a Performance Model to Implement a Superscalar CVA6

Thales built a precise performance model for the CVA6 RISC-V core to evaluate changes before touching RTL. The model achieved COREMARK performance results that were within 0.8% of the RTL, uncovering performance bottlenecks and informing the design of a dual-issue CVA6 core. Outcome? A 40% performance boost with just +7% power and +11% area. This shows how modeling can transform open hardware development.

Project Snapshot

How does performance modeling accelerate real hardware innovation in open RISC-V designs?

In this paper, Thales demonstrates a performance model of the CVA6 RISC-V processor, built to evaluate performance-related modifications before implementing them in RTL. 

By creating a precise cycle-based Python model (99.2% accuracy on Coremark) to detect and fix performance bugs, they guided the implementation of a dual-issue CVA6 core.

The result: +40% higher CoreMark/MHz performance with only a small power (+7%) and area (+11%) increase.

 
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