Projects | OpenHW

Projects

Core-V-Cores

System Verilog RTL source code for the CORE-V family of RISC-V cores

Programs

Program and project level documentation for all of OpenHW Group's projects including CORE-V RISC-V cores

Core-V-Verif

Functional verification project for the CORE-V family of RISC-V cores

OpenHW CVA6

Industrial and academic projects requiring access to either 32- or 64-bit, embedded or application class cores. The CVA6 can be synthesized for both FPGA and ASIC targets.

Latest release: none
Project status: Incubating

OpenHW Group CORE-V Cores

The tangible products produced by OpenHW Foundation CORE-V Cores includes: Documentation: complete user manual. Implementation: RTL model and synthesis scripts for both ASIC and FPGA implementations…

Latest release: 1.0
Project status: Incubating